1. Technical Field
The present invention relates to a method and system within a multiprocessor data processing system for testing the multiprocessor system, and in particular to generating a first and a second trace within the multiprocessing system during execution of a test program. Still more particularly, the present invention relates to a method and system for testing the system by, during execution of a test program, generating a first and a second trace within the system, where the first trace is generated by monitoring all events occurring at a first location and the second trace is generated by monitoring all events occurring at a second location.
2. Description of the Related Art
A multiprocessor data processing systems may include a plurality of processors and a shared main memory, where each processor includes its own cache. In such a multiprocessor system, maintaining cache coherency and consistency is important.
The term "coherency" refers to the ordering of competing storage access events from different processors. Competing storage access events are those events that attempt to store information into the same location. The term "consistency" refers to the ordering of all storage access events within a single processor.
Verifying that the multiprocessor system maintains cache coherency and consistency must be done as these multiprocessor data processing systems are designed. Verification is typically done by providing a testing device. The testing device compares the results obtained after execution of a test program within a particular model of the system under test with predicted results.
One testing device provides a functional simulator and comparator. The test program is applied to the functional simulator of the testing device which generates predicted results. The test program in this case is executed by to a simulator which simulates the model under test. Once the simulator, acting as the model under test, has completed execution of the test program, the testing device obtains the results of the test which are the values stored in registers, cache, and main memory within the testing device simulator. The predicted results include the values predicted to be stored in registers, cache, and memory for the model. The predicted results are compared to the actual results. This testing device is restricted to a comparison of values available only at the end of the processing of the test program. Interim values stored in registers, cache, and main memory are lost. As a result, storage access ordering of events and errors caused by race conditions which are due to competing accesses are not determined by the test device. In addition, the test program is restricted to performing stores only to non-overlapping bytes. This testing device may be used with a variety of multiprocessor systems and may be less expensive to implement. However, because of the limitations of this test device described above, a large number of errors may go undetected.
Another method is to provide a testing device which is functionally equivalent to the model under test. The state of the model under test is matched by the state of the testing device at all times during the test. A comparison is made between the states of the testing device and the states of the model. However, it is not often practical to provide such a testing device for each model which is to be tested. A testing device designed for one particular model could not be used for a different model. The design of the model may change frequently, thus causing increased time and cost in order to develop to a testing device for each model design. Although this test device is very accurate for a particular multiprocessor system, it cannot be used on a variety of systems. It is limited to the particular system for which it is designed. Therefore, when testing a variety of systems or different implementations of the same design, this testing device may be prohibitively costly and time consuming.
Therefore a need exists for a cost effective method and system for testing multiprocessor systems which may be quickly customized for a variety multiprocessor systems.